The present invention relates to an address latch enable signal control circuit for electronic memories. More particularly, the invention relates to an address latch signal control circuit for both volatile and nonvolatile memories which not only ensures correct address reading but also ensures certainty of the intention to acquire an address which is external to the memory.
It is known that volatile and permanent electronic memories point to one of their internal locations by using interposed structures, such as for example latch circuits or counters.
In order to operate correctly, these structures require suitable control signals which determine and allow the loading of a new address from outside the memory.
The control signal, usually known as ALE (Address Latch Enable), generally has several characteristics which are very important for its effectiveness and validity when it is necessary to operate in extreme conditions, such as for example those entailed by a high address acquisition rate, which introduces acquisition problems.
A first one of these characteristics is the duration of the control pulse. When this duration is too short, bad address capture conditions occur: at high rates, the pulse (control signal) is very narrow and address capture is unsteady.
A second characteristic is the filtering of noise-related pulses (spikes) which can lead to false and unintended address loadings.
A third characteristic of the control signal is to recognize authentic and non-authentic ALE pulses for the memory. For example, when a standby condition occurs, every activation of the ALE line is to be understood as being aimed at address capture activities on the part of another device that belongs to the system, but this address is not pertinent to the electronic memory being considered.
In normal and ideal operating conditions of the system, the above conditions, despite being stringent, are not difficult to meet, since it is sufficient to design them suitably during the construction of the system.
However, it is necessary to ensure that the ALE control signal is not independent of the other fundamental control signals of the memory, such as for example CE and RD.
For memories with an interleaved architecture, this last characteristic becomes particularly important, since synchronization among the various control signals introduces significant "sensitivities" which must be eliminated.
A first negative sensitivity is caused by return from a standby condition of the memory (i.e., when CEn switches from 1 to 0) while the ALE pulse is already active. In this situation, since the switching of the chip enable signal (CEn) occurs with a delay with respect to the ALE pulse, this causes a sort of "slicing" of the address capture pulse, consequently making said address capture critical.
If the switching delay of the CEn signal is excessive, this can even cause absence of the internal pulse (total suppression of the external pulse).
Another significant drawback occurs in the transition from the active step to the standby step (i.e., when the signal CEn switches from 0 to 1) when the ALE pulse is present. In this case, if the ALE pulse occurs too early with respect to the switching of the CEn signal, the external ALE pulse is interpreted incorrectly and, by generating an internal pulse, an unintended address capture occurs.